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PD -95993
IRF7555PBF
Trench Technology l Ultra Low On-Resistance l Dual P-Channel MOSFET l Very Small SOIC Package l Low Profile (<1.1mm) l Available in Tape & Reel l Lead-Free
l
HEXFET(R) Power MOSFET
S1 G1 S2 G2
1 8
D1 D1 D2 D2
2
7
VDSS = -20V
3
6
4
5
RDS(on) = 0.055
Top View
Description
New trench HEXFET(R) power MOSFETs from International Rectifier utilize advanced processing techniques to achieve extremely low on-resistance per silicon area. This benefit, combined with the ruggedized device design that HEXFET Power MOSFETs are well known for, provides the designer with an extremely efficient and reliable device for use in a wide variety of applications. The new Micro8TM package has half the footprint area of the standard SO-8. This makes the Micro8 an ideal package for applications where printed circuit board space is at a premium. The low profile (<1.1mm) of the Micro8 will allow it to fit easily into extremely thin application environments such as portable electronics and PCMCIA cards.
Micro8TM
Absolute Maximum Ratings
Parameter
VDS ID @ TA = 25C ID @ TA = 70C IDM PD @TA = 25C PD @TA = 70C VGS EAS dv/dt TJ , TSTG Drain-Source Voltage Continuous Drain Current, VGS @ -4.5V Continuous Drain Current, VGS @ -4.5V Pulsed Drain Current Maximum Power Dissipation Maximum Power Dissipation Linear Derating Factor Gate-to-Source Voltage Single Pulse Avalanche Energy Peak Diode Recovery dv/dt Junction and Storage Temperature Range Soldering Temperature, for 10 seconds
Max.
-20 -4.3 -3.4 -34 1.25 0.8 10 12 36 1.1 -55 to + 150 240 (1.6mm from case)
Units
V A W W mW/C V mJ V/ns C
Thermal Resistance
Parameter
RJA
Max.
Units
100 C/W
Maximum Junction-to-Ambient
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1
2/22/05
IRF7555PBF
Electrical Characteristics @ TJ = 25C (unless otherwise specified)
V(BR)DSS
V(BR)DSS/TJ
Parameter Drain-to-Source Breakdown Voltage Breakdown Voltage Temp. Coefficient Static Drain-to-Source On-Resistance Gate Threshold Voltage Forward Transconductance Drain-to-Source Leakage Current Gate-to-Source Forward Leakage Gate-to-Source Reverse Leakage Total Gate Charge Gate-to-Source Charge Gate-to-Drain ("Miller") Charge Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Input Capacitance Output Capacitance Reverse Transfer Capacitance
RDS(on) VGS(th) gfs IDSS IGSS Qg Qgs Qgd td(on) tr td(off) tf Ciss Coss Crss
Min. -20 --- --- -0.60 2.5 --- --- --- --- --- --- --- --- --- --- --- --- --- ---
Typ. Max. Units Conditions --- --- V VGS = 0V, ID = -250A -0.005 --- V/C Reference to 25C, ID = -1mA --- 0.055 VGS = -4.5V, ID = -4.3A --- 0.105 VGS = -2.5V, ID = -3.4A --- -1.2 V VDS = VGS, ID = -250A --- --- S VDS = -10V, ID = -0.8A --- -1.0 VDS = -16V, VGS = 0V A --- -25 VDS = -16V, VGS = 0V, TJ = 125C --- -100 VGS = -12V nA --- 100 VGS = 12V 10 15 ID = -3.0A 2.1 3.1 nC VDS = -10V 2.5 3.7 VGS = -5.0V 10 --- VDD = -10V 46 --- ID = -2.0A ns 60 --- RG = 6.0 64 --- RD = 5.0 1066 --- VGS = 0V 402 --- pF VDS = -10V 126 --- = 1.0MHz
Source-Drain Ratings and Characteristics
IS
ISM
VSD trr Qrr
Parameter Continuous Source Current (Body Diode) Pulsed Source Current (Body Diode) Diode Forward Voltage Reverse Recovery Time Reverse Recovery Charge
Min. Typ. Max. Units --- --- --- --- 54 41 -1.3 A -34 -1.2 82 61 V ns nC
Conditions MOSFET symbol showing the G integral reverse p-n junction diode. TJ = 25C, IS = -1.6A, VGS = 0V TJ = 25C, IF = -2.5A di/dt = -100A/s
D
S
Notes:
Repetitive rating; pulse width limited by
max. junction temperature.
Surface mounted on FR-4 board, t 10sec. Starting TJ = 25C, L = 8.0mH
RG = 25, I AS = -3.0A.
ISD -2.0A, di/dt -140A/s, VDD V(BR)DSS,
TJ 150C
Pulse width 300s; duty cycle 2%.
2
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IRF7555PBF
100
-I D , Drain-to-Source Current (A)
10
-I D , Drain-to-Source Current (A)
VGS -7.50V -5.00V -4.00V -3.50V -3.00V -2.50V -2.00V BOTTOM -1.50V TOP
100
VGS -7.50V -5.00V -4.00V -3.50V -3.00V -2.50V -2.00V BOTTOM -1.50V TOP
10
1
1
-1.50V
-1.50V
0.1 0.1
20s PULSE WIDTH TJ = 25 C
1 10 100
0.1 0.1
20s PULSE WIDTH TJ = 150 C
1 10 100
-VDS , Drain-to-Source Voltage (V)
-VDS , Drain-to-Source Voltage (V)
Fig 1. Typical Output Characteristics
Fig 2. Typical Output Characteristics
100
2.0
TJ = 25 C
RDS(on) , Drain-to-Source On Resistance (Normalized)
ID = -4.3A
-I D , Drain-to-Source Current (A)
1.5
TJ = 150 C
10
1.0
0.5
1 1.0
V DS = -15V 20s PULSE WIDTH 2.0 3.0 4.0 5.0
0.0 -60 -40 -20
VGS = -4.5V
0 20 40 60 80 100 120 140 160
-VGS , Gate-to-Source Voltage (V)
TJ , Junction Temperature ( C)
Fig 3. Typical Transfer Characteristics
Fig 4. Normalized On-Resistance Vs. Temperature
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IRF7555PBF
1600
-VGS , Gate-to-Source Voltage (V)
VGS Ciss Crss Coss
= 0V, f = 1MHz = Cgs + Cgd , Cds SHORTED = Cgd = Cds + Cgd
15
ID = -4.3A -4.5A
12
C, Capacitance (pF)
1200
Ciss
VDS =-10V
9
800
6
400
Coss Crss
0 1 10 100
3
0
0
4
8
12
16
20
24
-VDS, Drain-to-Source Voltage (V)
Q G , Total Gate Charge (nC)
Fig 5. Typical Capacitance Vs. Drain-to-Source Voltage
Fig 6. Typical Gate Charge Vs. Gate-to-Source Voltage
100
100
-ISD , Reverse Drain Current (A)
OPERATION IN THIS AREA LIMITED BY RDS(on)
10us
-ID , Drain Current (A) I
10
10
100us
TJ = 150 C TJ = 25 C
1
1ms
1
10ms
0.1 0.0
V GS = 0 V
0.4 0.8 1.2 1.6 2.0 2.4
0.1 0.1
TC = 25 C TJ = 150 C Single Pulse
1 10 100
-VSD ,Source-to-Drain Voltage (V)
-VDS , Drain-to-Source Voltage (V)
Fig 7. Typical Source-Drain Diode Forward Voltage
Fig 8. Maximum Safe Operating Area
4
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IRF7555PBF
5.0
100
EAS , Single Pulse Avalanche Energy (mJ)
4.0
80
ID -1.3A -2.4A BOTTOM -3.0A TOP
-ID , Drain Current (A)
3.0
60
2.0
40
1.0
20
0.0
25
50
75
100
125
150
0
TC , Case Temperature ( C)
25
50
75
100
125
150
Starting TJ , Junction Temperature ( C)
Fig 9. Maximum Drain Current Vs. Case Temperature
Fig 10. Maximum Avalanche Energy Vs. Drain Current
1000
Thermal Response (Z thJA )
100 D = 0.50 0.20 10 0.10 0.05 0.02 0.01 1 SINGLE PULSE (THERMAL RESPONSE) PDM t1 t2 Notes: 1. Duty factor D = t 1 / t 2 2. Peak T J = P DM x Z thJA + TA 0.001 0.01 0.1 1 10 100
0.1 0.0001
t1 , Rectangular Pulse Duration (sec)
Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Ambient
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IRF7555PBF
Current Regulator Same Type as D.U.T.
50K
QG QGS VG QGD
12V
.2F .3F
VGS
-3mA
IG
ID
Charge
Current Sampling Resistors
Fig 12a. Basic Gate Charge Waveform
Fig 12b. Gate Charge Test Circuit
Fig 13a. Switching Time Test Circuit
td(on) tr t d(off) tf
VGS 10%
90% VDS
Fig 13b. Switching Time Waveforms
6
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+
D.U.T.
+
VDS
-
IRF7555PBF
Peak Diode Recovery dv/dt Test Circuit
+
Circuit Layout Considerations * Low Stray Inductance * Ground Plane * Low Leakage Inductance Current Transformer
+ +
-
* dv/dt controlled by RG * ISD controlled by Duty Factor "D" * D.U.T. - Device Under Test
+ -
*
Reverse Polarity for P-Channel ** Use P-Channel Driver for P-Channel Measurements
Driver Gate Drive P.W. Period D=
P.W. Period VGS=10V
D.U.T. ISD Waveform Reverse Recovery Current Body Diode Forward Current di/dt D.U.T. VDS Waveform Diode Recovery dv/dt
VDD
Re-Applied Voltage Inductor Curent
Body Diode
Forward Drop
Ripple 5%
ISD
*** VGS = 5.0V for Logic Level and 3V Drive Devices Fig -14 For P Channel HEXFETS
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IRF7555PBF
Micro8 Package Outline
Dimensions are shown in milimeters (inches)
LEAD ASSIGNMENTS D -B3 DDDD 8765 3 E -A1234 SSSG S1 G1 S2 G2 8765 H 0.25 (.010) M A M SINGLE 1234 DUAL 1234 D1 D1 D2 D2 8765
DIM INCHES MIN MAX MILLIMETERS MIN MAX
A A1 B C D e e1 E H L
.036 .004 .010 .005 .116
.044 .008 .014 .007 .120
0.91 0.10 0.25 0.13 2.95
1.11 0.20 0.36 0.18 3.05
.0256 BASIC .0128 BASIC .116 .188 .016 0 .120 .198 .026 6
0.65 BASIC 0.33 BASIC 2.95 4.78 0.41 0 3.05 5.03 0.66 6
e 6X e1 A -CB 8X 0.08 (.003) M A1 C AS BS 0.10 (.004) L 8X C 8X
RECOMMENDED FOOTPRINT 1.04 ( .041 ) 8X 0.38 8X ( .015 )
3.20 ( .126 )
4.24 5.28 ( .167 ) ( .208 )
NOTES: 1 DIMENSIONING AND TOLERANCING PER ANSI Y14.5M-1982. 2 CONTROLLING DIMENSION : INCH. 3 DIMENSIONS DO NOT INCLUDE MOLD FLASH.
0.65 6X ( .0256 )
Micro8 Part Marking Information
EXAMPLE: T HIS IS AN IRF7501
LOT CODE (XX)
DAT E CODE (YW) - S ee table below Y = YEAR W = WEEK P = DES IGNAT ES LEAD - FREE PRODUCT (OPTIONAL)
PART NUMBER
WW = (1-26) IF PRECEDED BY LAS T DIGIT OF CALENDAR YEAR YEAR 2001 2002 2003 2004 2005 2006 2007 2008 2009 2010 Y 1 2 3 4 5 6 7 8 9 0 WORK WEEK 01 02 03 04 W A B C D
WW = (27-52) IF PRECEDED BY A LETT ER YEAR 2001 2002 2003 2004 2005 2006 2007 2008 2009 2010 Y A B C D E F G H J K WORK WEEK 27 28 29 30 W A B C D
24 25 26
X Y Z
50 51 52
X Y Z
8
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IRF7555PBF
Micro8 Tape & Reel Information
Dimensions are shown in millimeters (inches)
TERMINAL NUMBER 1
12.3 ( .484 ) 11.7 ( .461 )
8.1 ( .318 ) 7.9 ( .312 )
FEED DIRECTION
NOTES: 1. OUTLINE CONFORMS TO EIA-481 & EIA-541. 2. CONTROLLING DIMENSION : MILLIMETER.
330.00 (12.992) MAX.
14.40 ( .566 ) 12.40 ( .488 ) NOTES : 1. CONTROLLING DIMENSION : MILLIMETER. 2. OUTLINE CONFORMS TO EIA-481 & EIA-541.
Data and specifications subject to change without notice. This product has been designed and qualified for the Consumer market. Qualifications Standards can be found on IR's Web site.
IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105 TAC Fax: (310) 252-7903 Visit us at www.irf.com for sales contact information. 02/05
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